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SX1223
5.2.2 Other Settings
The tables below give the definition of all the parameters of the configuration registers besides the working modes.
Add Bits
0 4-2
PA2
0
0
0
0
1
1
1
1
PA1
0
0
1
1
0
0
1
1
PA0
0
1
0
1
0
1
0
1
State
21dB attenuation
18dB attenuation
15dB attenuation
12dB attenuation
9dB attenuation
6dB attenuation
3dB attenuation
Max output (default)
Table 9: Power amplifier output power
Add
Bit ClkOut_en
State
Comments
0
1
0
ClkOut off
Output is 0 volt on pin CLKOUT.
A clock at XCO frequency divided by 16 is
1
ClkOut on
available on pin CLKOUT. (default)
Table 10: Output clock
Add
0
Bit
0
Sync_en
0
State
DCLK pin off
Comments
Transparent transmission of data
Bit-clock
is generated by transceiver
1
DCLK pin on
(default)
Table 11: Synchronizer mode
Add
Bit Modulation1 Modulation0 State
Comments
1
7-6
0 0
0
1
1
0
1
1
Closed loop VCO-modulation (mw1)
Open loop VCO-modulation (mw2)
Modulation by M, N and A (mw3)
Not used
VCO is phase-locked
VCO is free-running
(default)
Modulation inside PLL
Table 12: Modulation mode
Add
1
Bit
5
FreqBand
0
1
Comments
RF frequency 425-475 MHz
RF frequency 850-950 MHz (default)
Table 13: Frequency band
Add
1
Bit
4
XCOcap_en
0
Comments
Internal capacitors for the crystal oscillator turned off
Internal capacitors for the crystal oscillator turned on, external capacitors not needed
1
(default)
Table 14: XCO internal capacitor
? Semtech 2007
17
www.semtech.com
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